1. Field of the Invention
The present invention relates in general to the field of electronics, and more specifically to a system and method related to cascode configured switching using at least one low breakdown voltage internal, integrated circuit switch to control at least one high breakdown voltage external switch.
2. Description of the Related Art
Systems often modulate conductivity of one or more semiconductor-based switches to control current through the switches. For example, switching power converters utilize a switch to control conversion of alternating current (AC) voltages to direct current (DC) voltages or DC-to-DC. Switches are also often used to control regulated current devices such as light emitting diodes (LEDs). Semiconductor-based switches can be categorized as low voltage switches and high voltage switches relative to each other. For example, semiconductor-based switches have breakdown voltages. Breakdown occurs when a voltage greater than the breakdown voltage causes avalanche multiplication of carriers in the switch. For example, in at least one embodiment, the breakdown voltage of a complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) refers to a maximum allowable drain-to-source voltage of the CMOS FET beyond which breakdown of the CMOS FET occurs. In at least one embodiment, the breakdown voltage of a bi-polar junction transistor (BJT) refers to a maximum allowable collector-to-emitter voltage of the BJT beyond which breakdown of the BJT occurs.
FIG. 1 represents a power control system 100, which includes switching power converter 102. In at least one embodiment, switching power converter operates in a continuous conduction mode (CCM). Voltage source 101 supplies an alternating current (AC) input voltage VIN to a full bridge diode rectifier 103. The voltage source 101 is, for example, a public utility, and the AC voltage VIN is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/220 V line voltage in Europe. The rectifier 103 rectifies the input voltage VIN and supplies a rectified, time-varying, line input voltage VX to the switching power converter.
The switching power converter 102 includes at least two switching operations, i.e. controlling field effect transistor (FET) 108 to provide power factor correction and controlling FET 108 to provide regulation of link voltage VLINK. The inductor current iL ramps ‘up’ when FET 108 conducts, i.e. is “ON”. The inductor current iL ramps down when FET 108 is nonconductive, i.e. is “OFF”, and supplies current iL to recharge capacitor 106. The time period during which inductor current iL ramps down is commonly referred to as the “inductor flyback time”. Diode 111 prevents reverse current flow into inductor 110. In at least one embodiment, control signal CS0 is a pulse width modulated signal, and FET 108 is an n-channel FET. In this embodiment, control signal CS0 is a gate voltage of FET 108, and FET 108 conducts when the pulse width of CS0 is high. Thus, the ‘on-time’ of FET 108 is determined by the pulse width of control signal CS0. In at least one embodiment, the switching power converter 102 operates in CCM, i.e. ramp up time of the inductor current iL plus the inductor flyback time is greater than or equal to the period of the control signal CS0.
In at least one embodiment, switching power converter 102 boosts a 110-120 V rectified input voltage VX to a higher link voltage VLINK, such as 200-400V. Accordingly, FET 108 is fabricated to have a breakdown voltage sufficient to accommodate the controlled current iCCT and voltage drops across FET 108 associated with the high input voltage VX and higher link voltage VLINK. FET 108 is a high breakdown voltage device fabricated using a “high” voltage process. In at least one embodiment, FET 108 has a breakdown voltage greater than or equal to 30V and at least sufficient to accommodate operating characteristics of switching power converter 102. In at least one embodiment, power factor correction (PFC) and output voltage controller 114 is an integrated circuit and is fabricated using a low voltage process that is insufficient to fabricate a switch with a sufficiently high breakdown voltage to control the controlled current iCCT. Thus, FET 108 is located external to PFC and output voltage controller 114. As subsequently described in more detail, PFC and output voltage controller 114 generates a pulse width modulated control signal CS0 to control conductivity of FET 108. In at least one embodiment, FET 108 is a FET, and control signal CS0 is a gate voltage.
Switching power converter 102 includes current sense resistor 109. Current sense circuit 109 can be any circuit that senses the switch controlled current iCC. The switch controlled current iCC generates a sense voltage VSEN across current sense resistor 109. The PFC and output voltage controller 114 receives the sense voltage VSEN. The resistance R of sense resistor 109 is known. The sense voltage VSEN is directly related to switch controlled current iCC via Ohm's law, i.e. VSEN=iCC·R. “R” represents a resistance value of sense resistor 109, and the value of R is a matter of design choice. In at least one embodiment, PFC and output voltage controller 114 utilizes the sense voltage VSEN and sensing two signals, namely, the line input voltage VX and the capacitor voltage/output voltage VLINK to generate the pulse width and duty cycle of control signal CS0.
Capacitor 106 supplies stored energy to load 112. The capacitor 106 is sufficiently large so as to maintain a substantially constant output voltage VLINK, as established by a switch state controller 114 (as discussed in more detail below). The output voltage VLINK remains substantially constant during constant load conditions. However, as load conditions change, the output voltage VLINK changes. The switch state controller 114 responds to the changes in VLINK and adjusts the control signal CS0 to restore a substantially constant output voltage as quickly as possible. The switch state controller 114 includes a small capacitor 115 to filter any high frequency signals from the line input voltage VX.
The switch state controller 114 of power control system 100 controls FET 108 and, thus, controls power factor correction (PFC) and regulates output power of the switching power converter 102. The goal of power factor correction technology is to make the switching power converter 102 appear resistive to the voltage source 101. Thus, the switch state controller 114 attempts to control the inductor current iL so that the average inductor current iL is linearly and directly related to the line input voltage VX. A CCM PFC controller, model number UCC28019A, available from Texas Instruments, Inc., Texas, USA is an example of switch state controller 114. The switch state controller 114 controls the pulse width (PW) and period (TT) of control signal CS0. To regulate the amount of energy transferred and maintain a power factor close to one, switch state controller 114 varies the period of control signal CS0 so that the input current iL tracks the changes in input voltage VX and holds the output voltage VLINK constant. Thus, as the input voltage VX increases, switch state controller 114 increases the period TT of control signal CS0, and as the input voltage VX decreases, switch state controller 114 decreases the period of control signal CS0. At the same time, the pulse width PW of control signal CS0 is adjusted to maintain a constant duty cycle (D) of control signal CS0, and, thus, hold the output voltage VLINK constant.
In at least one embodiment, the switch state controller 114 updates the control signal CS0 at a frequency much greater than the frequency of input voltage VX. The frequency of input voltage VX is generally 50-60 Hz. The frequency 1/TT of control signal CS0 is, for example, between 20 kHz and 130 kHz. Frequencies at or above 20 kHz avoid audio frequencies and frequencies at or below 130 kHz avoid significant switching inefficiencies while still maintaining good power factor, e.g. between 0.9 and 1, and an approximately constant output voltage VLINK.
As previously described, FET 108 is fabricated using a higher breakdown voltage process relative to a process used to fabricate PFC and output voltage controller 114. Accordingly, FET 108 is located external to PFC and output voltage controller 114 because the processes used to fabricate devices in PFC and output voltage controller 114 are incompatible with the process used to fabricate FET 108. Higher voltage switches have higher breakdown voltages. However, high voltage FET 108 has disadvantages relative to a low breakdown voltage switch. For example, relative to lower breakdown voltage switches, FET 108 requires more charge to change conduction state and has higher parasitic diode and capacitance related characteristics. Additionally, turning FET 108 “on” and “off” requires charging and discharging a gate of FET 108, and the charge on gate of FET 108 is discharged through a ground reference node and is therefore lost.